/*==============================================================================
 Copyright (c) 2015-2018 Qualcomm Technologies, Inc.
 All Rights Reserved.
 Confidential and Proprietary - Qualcomm Technologies, Inc.
==============================================================================*/
#ifndef TITAN170_APU32Q2N7S1V1_2_CL36_H
#define TITAN170_APU32Q2N7S1V1_2_CL36_H

#ifdef _MSC_VER
#ifdef ERROR
#undef ERROR
#endif // ERROR
#endif // _MSC_VER

/*----------------------------------------------------------------------
        Offset and Mask
----------------------------------------------------------------------*/

#define APU32Q2N7S1V1_2_CL36_REGS_FIRST 0x0

#define APU32Q2N7S1V1_2_CL36_REGS_LAST 0x10e0

#define APU32Q2N7S1V1_2_CL36_REGS_COUNT 0x39

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_GCR0 0x0  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_GCR0_AADEN_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_GCR0_AADEN_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_GCR0_UNUSED0_MASK 0xfffffffe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_GCR0_UNUSED0_SHIFT 0x1

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0 0x8  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_SCFGERE_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_SCFGERE_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_SCLERE_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_SCLERE_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_SCFGEIE_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_SCFGEIE_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_SCLEIE_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_SCLEIE_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_UNUSED0_MASK 0xf0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_UNUSED0_SHIFT 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_DYNAMIC_CLK_EN_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_DYNAMIC_CLK_EN_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_UNUSED1_MASK 0xfffffe00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0_UNUSED1_SHIFT 0x9

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0 0x10  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_CFGERE_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_CFGERE_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_CLERE_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_CLERE_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_CFGEIE_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_CFGEIE_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_CLEIE_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_CLEIE_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_UNUSED0_MASK 0x70
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_UNUSED0_SHIFT 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_VMIDEN_MASK 0x80
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_VMIDEN_SHIFT 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_DYNAMIC_CLK_EN_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_DYNAMIC_CLK_EN_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_UNUSED1_MASK 0xfffffe00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0_UNUSED1_SHIFT 0x9

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RPU_ACR0 0x20  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RPU_ACR0_SUVMID_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RPU_ACR0_SUVMID_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_GCR0 0x80  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_GCR0_QAD0DEN_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_GCR0_QAD0DEN_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_GCR0_UNUSED0_MASK 0xfffffffe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_GCR0_UNUSED0_SHIFT 0x1

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0 0x90  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_CFGERE_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_CFGERE_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_CLERE_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_CLERE_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_CFGEIE_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_CFGEIE_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_CLEIE_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_CLEIE_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_UNUSED0_MASK 0xf0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_UNUSED0_SHIFT 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_DYNAMIC_CLK_EN_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_DYNAMIC_CLK_EN_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_UNUSED1_MASK 0xfffffe00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0_UNUSED1_SHIFT 0x9

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_GCR0 0x100  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_GCR0_QAD1DEN_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_GCR0_QAD1DEN_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_GCR0_UNUSED0_MASK 0xfffffffe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_GCR0_UNUSED0_SHIFT 0x1

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0 0x110  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_CFGERE_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_CFGERE_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_CLERE_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_CLERE_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_CFGEIE_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_CFGEIE_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_CLEIE_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_CLEIE_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_UNUSED0_MASK 0xf0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_UNUSED0_SHIFT 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_DYNAMIC_CLK_EN_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_DYNAMIC_CLK_EN_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_UNUSED1_MASK 0xfffffe00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0_UNUSED1_SHIFT 0x9

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR3 0x3ec  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR3_NVMID_MASK 0xff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR3_NVMID_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR3_MV_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR3_MV_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR3_PT_MASK 0x200
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR3_PT_SHIFT 0x9
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR3_UNUSED0_MASK 0xfffffc00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR3_UNUSED0_SHIFT 0xa

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2 0x3f0  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2_NUM_QAD_MASK 0xf
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2_NUM_QAD_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2_UNUSED0_MASK 0xf0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2_UNUSED0_SHIFT 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2_VMIDACR_EN_MASK 0xff00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2_VMIDACR_EN_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2_SEC_EN_MASK 0xff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2_SEC_EN_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2_NONSEC_EN_MASK 0xff000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2_NONSEC_EN_SHIFT 0x18

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1 0x3f4  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1_UNUSED0_MASK 0xffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1_UNUSED0_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1_CONFIG_ADDR_WIDTH_MASK 0x3f0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1_CONFIG_ADDR_WIDTH_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1_UNUSED1_MASK 0xc00000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1_UNUSED1_SHIFT 0x16
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1_CLIENT_ADDR_WIDTH_MASK 0x3f000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1_CLIENT_ADDR_WIDTH_SHIFT 0x18
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1_UNUSED2_MASK 0xc0000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1_UNUSED2_SHIFT 0x1e

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0 0x3f8  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_XPUTYPE_MASK 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_XPUTYPE_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_UNUSED0_MASK 0x1c
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_UNUSED0_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_CLIENTREQ_HALT_ACK_HW_EN_MASK 0x20
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_CLIENTREQ_HALT_ACK_HW_EN_SHIFT 0x5
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_UNUSED1_MASK 0xffc0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_UNUSED1_SHIFT 0x6
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_NRG_MASK 0x3ff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_NRG_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_UNUSED2_MASK 0xfc000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0_UNUSED2_SHIFT 0x1a

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_REV 0x3fc  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_REV_STEP_MASK 0xffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_REV_STEP_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_REV_MINOR_MASK 0xfff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_REV_MINOR_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_REV_MAJOR_MASK 0xf0000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_REV_MAJOR_SHIFT 0x1c

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_FREESTATUS0 0x500  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_FREESTATUS0_RGFREESTATUS_MASK 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_FREESTATUS0_RGFREESTATUS_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_FREESTATUS0_UNUSED0_MASK 0xfffffffc
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_FREESTATUS0_UNUSED0_SHIFT 0x2

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_SEAR0 0x800  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SEAR0_ADDR_31_0_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SEAR0_ADDR_31_0_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_SEAR1 0x804  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SEAR1_ADDR_63_32_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SEAR1_ADDR_63_32_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR 0x808  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR_CFG_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR_CFG_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR_CLIENT_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR_CLIENT_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR_CFGMULTI_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR_CFGMULTI_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR_CLMULTI_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR_CLMULTI_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR_UNUSED0_MASK 0xfffffff0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR_UNUSED0_SHIFT 0x4

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE 0x80c  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE_CFG_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE_CFG_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE_CLIENT_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE_CLIENT_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE_CFGMULTI_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE_CFGMULTI_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE_CLMULTI_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE_CLMULTI_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE_UNUSED0_MASK 0xfffffff0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE_UNUSED0_SHIFT 0x4

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0 0x810  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_XPROTNS_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_XPROTNS_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_AWRITE_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_AWRITE_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_XINST_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_XINST_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_XPRIV_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_XPRIV_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_UNUSED0_MASK 0xf0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_UNUSED0_SHIFT 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_QAD_MASK 0xff00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_QAD_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_ALEN_MASK 0xff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_ALEN_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_ASIZE_MASK 0x7000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_ASIZE_SHIFT 0x18
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_UNUSED1_MASK 0x18000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_UNUSED1_SHIFT 0x1b
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_BURSTLEN_MASK 0x20000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_BURSTLEN_SHIFT 0x1d
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_AC_MASK 0x40000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_AC_SHIFT 0x1e
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_UNUSED2_MASK 0x80000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0_UNUSED2_SHIFT 0x1f

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1 0x814  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1_MID_MASK 0xff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1_MID_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1_PID_MASK 0x1f00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1_PID_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1_BID_MASK 0xe000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1_BID_SHIFT 0xd
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1_VMID_MASK 0xff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1_VMID_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1_TID_MASK 0xff000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1_TID_SHIFT 0x18

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2 0x818  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_MEMTYPE_MASK 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_MEMTYPE_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_UNUSED0_MASK 0x78
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_UNUSED0_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_TRANSIENT_MASK 0x80
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_TRANSIENT_SHIFT 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_NOALLOCATE_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_NOALLOCATE_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_OOOWR_MASK 0x200
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_OOOWR_SHIFT 0x9
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_OOORD_MASK 0x400
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_OOORD_SHIFT 0xa
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_ORDEREDWR_MASK 0x800
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_ORDEREDWR_SHIFT 0xb
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_ORDEREDRD_MASK 0x1000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_ORDEREDRD_SHIFT 0xc
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_PORTMREL_MASK 0x2000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_PORTMREL_SHIFT 0xd
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_INNERWRITETHROUGH_MASK 0x4000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_INNERWRITETHROUGH_SHIFT 0xe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_INNERTRANSIENT_MASK 0x8000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_INNERTRANSIENT_SHIFT 0xf
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_INNERSHARED_MASK 0x10000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_INNERSHARED_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_INNERCACHEABLE_MASK 0x20000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_INNERCACHEABLE_SHIFT 0x11
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_INNERNOALLOCATE_MASK 0x40000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_INNERNOALLOCATE_SHIFT 0x12
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_WRITETHROUGH_MASK 0x80000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_WRITETHROUGH_SHIFT 0x13
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_SHARED_MASK 0x100000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_SHARED_SHIFT 0x14
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_FULL_MASK 0x200000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_FULL_SHIFT 0x15
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_EXCLUSIVE_MASK 0x400000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_EXCLUSIVE_SHIFT 0x16
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_ERROR_MASK 0x800000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_ERROR_SHIFT 0x17
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_EARLYWRRESP_MASK 0x1000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_EARLYWRRESP_SHIFT 0x18
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_DEVICE_TYPE_MASK 0x6000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_DEVICE_TYPE_SHIFT 0x19
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_DEVICE_MASK 0x8000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_DEVICE_SHIFT 0x1b
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_CACHEABLE_MASK 0x10000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_CACHEABLE_SHIFT 0x1c
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_BURST_MASK 0x20000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_BURST_SHIFT 0x1d
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_BAR_MASK 0xc0000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2_BAR_SHIFT 0x1e

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_EAR0 0x880  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_EAR0_ADDR_31_0_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_EAR0_ADDR_31_0_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_EAR0 0x880  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_EAR0_ADDR_31_0_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_EAR0_ADDR_31_0_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_EAR0 0x880  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_EAR0_ADDR_31_0_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_EAR0_ADDR_31_0_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_EAR1 0x884  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_EAR1_ADDR_63_32_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_EAR1_ADDR_63_32_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_EAR1 0x884  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_EAR1_ADDR_63_32_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_EAR1_ADDR_63_32_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_EAR1 0x884  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_EAR1_ADDR_63_32_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_EAR1_ADDR_63_32_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR 0x888  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR_CFG_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR_CFG_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR_CLIENT_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR_CLIENT_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR_CFGMULTI_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR_CFGMULTI_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR_CLMULTI_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR_CLMULTI_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR_UNUSED0_MASK 0xfffffff0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR_UNUSED0_SHIFT 0x4

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR 0x888  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR_CFG_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR_CFG_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR_CLIENT_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR_CLIENT_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR_CFGMULTI_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR_CFGMULTI_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR_CLMULTI_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR_CLMULTI_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR_UNUSED0_MASK 0xfffffff0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR_UNUSED0_SHIFT 0x4

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR 0x888  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR_CFG_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR_CFG_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR_CLIENT_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR_CLIENT_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR_CFGMULTI_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR_CFGMULTI_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR_CLMULTI_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR_CLMULTI_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR_UNUSED0_MASK 0xfffffff0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR_UNUSED0_SHIFT 0x4

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE 0x88c  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE_CFG_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE_CFG_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE_CLIENT_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE_CLIENT_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE_CFGMULTI_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE_CFGMULTI_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE_CLMULTI_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE_CLMULTI_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE_UNUSED0_MASK 0xfffffff0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE_UNUSED0_SHIFT 0x4

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE 0x88c  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE_CFG_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE_CFG_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE_CLIENT_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE_CLIENT_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE_CFGMULTI_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE_CFGMULTI_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE_CLMULTI_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE_CLMULTI_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE_UNUSED0_MASK 0xfffffff0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE_UNUSED0_SHIFT 0x4

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE 0x88c  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE_CFG_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE_CFG_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE_CLIENT_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE_CLIENT_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE_CFGMULTI_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE_CFGMULTI_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE_CLMULTI_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE_CLMULTI_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE_UNUSED0_MASK 0xfffffff0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE_UNUSED0_SHIFT 0x4

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0 0x890  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_XPROTNS_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_XPROTNS_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_AWRITE_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_AWRITE_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_XINST_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_XINST_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_XPRIV_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_XPRIV_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_UNUSED0_MASK 0xf0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_UNUSED0_SHIFT 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_QAD_MASK 0xff00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_QAD_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_ALEN_MASK 0xff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_ALEN_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_ASIZE_MASK 0x7000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_ASIZE_SHIFT 0x18
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_UNUSED1_MASK 0x18000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_UNUSED1_SHIFT 0x1b
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_BURSTLEN_MASK 0x20000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_BURSTLEN_SHIFT 0x1d
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_AC_MASK 0x40000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_AC_SHIFT 0x1e
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_UNUSED2_MASK 0x80000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0_UNUSED2_SHIFT 0x1f

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0 0x890  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_XPROTNS_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_XPROTNS_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_AWRITE_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_AWRITE_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_XINST_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_XINST_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_XPRIV_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_XPRIV_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_UNUSED0_MASK 0xf0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_UNUSED0_SHIFT 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_QAD_MASK 0xff00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_QAD_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_ALEN_MASK 0xff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_ALEN_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_ASIZE_MASK 0x7000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_ASIZE_SHIFT 0x18
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_UNUSED1_MASK 0x18000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_UNUSED1_SHIFT 0x1b
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_BURSTLEN_MASK 0x20000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_BURSTLEN_SHIFT 0x1d
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_AC_MASK 0x40000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_AC_SHIFT 0x1e
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_UNUSED2_MASK 0x80000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0_UNUSED2_SHIFT 0x1f

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0 0x890  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_XPROTNS_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_XPROTNS_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_AWRITE_MASK 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_AWRITE_SHIFT 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_XINST_MASK 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_XINST_SHIFT 0x2
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_XPRIV_MASK 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_XPRIV_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_UNUSED0_MASK 0xf0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_UNUSED0_SHIFT 0x4
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_QAD_MASK 0xff00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_QAD_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_ALEN_MASK 0xff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_ALEN_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_ASIZE_MASK 0x7000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_ASIZE_SHIFT 0x18
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_UNUSED1_MASK 0x18000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_UNUSED1_SHIFT 0x1b
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_BURSTLEN_MASK 0x20000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_BURSTLEN_SHIFT 0x1d
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_AC_MASK 0x40000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_AC_SHIFT 0x1e
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_UNUSED2_MASK 0x80000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0_UNUSED2_SHIFT 0x1f

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1 0x894  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1_MID_MASK 0xff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1_MID_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1_PID_MASK 0x1f00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1_PID_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1_BID_MASK 0xe000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1_BID_SHIFT 0xd
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1_VMID_MASK 0xff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1_VMID_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1_TID_MASK 0xff000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1_TID_SHIFT 0x18

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1 0x894  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1_MID_MASK 0xff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1_MID_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1_PID_MASK 0x1f00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1_PID_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1_BID_MASK 0xe000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1_BID_SHIFT 0xd
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1_VMID_MASK 0xff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1_VMID_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1_TID_MASK 0xff000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1_TID_SHIFT 0x18

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1 0x894  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1_MID_MASK 0xff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1_MID_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1_PID_MASK 0x1f00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1_PID_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1_BID_MASK 0xe000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1_BID_SHIFT 0xd
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1_VMID_MASK 0xff0000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1_VMID_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1_TID_MASK 0xff000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1_TID_SHIFT 0x18

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2 0x898  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_MEMTYPE_MASK 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_MEMTYPE_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_UNUSED0_MASK 0x78
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_UNUSED0_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_TRANSIENT_MASK 0x80
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_TRANSIENT_SHIFT 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_NOALLOCATE_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_NOALLOCATE_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_OOOWR_MASK 0x200
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_OOOWR_SHIFT 0x9
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_OOORD_MASK 0x400
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_OOORD_SHIFT 0xa
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_ORDEREDWR_MASK 0x800
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_ORDEREDWR_SHIFT 0xb
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_ORDEREDRD_MASK 0x1000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_ORDEREDRD_SHIFT 0xc
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_PORTMREL_MASK 0x2000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_PORTMREL_SHIFT 0xd
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_INNERWRITETHROUGH_MASK 0x4000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_INNERWRITETHROUGH_SHIFT 0xe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_INNERTRANSIENT_MASK 0x8000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_INNERTRANSIENT_SHIFT 0xf
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_INNERSHARED_MASK 0x10000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_INNERSHARED_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_INNERCACHEABLE_MASK 0x20000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_INNERCACHEABLE_SHIFT 0x11
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_INNERNOALLOCATE_MASK 0x40000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_INNERNOALLOCATE_SHIFT 0x12
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_WRITETHROUGH_MASK 0x80000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_WRITETHROUGH_SHIFT 0x13
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_SHARED_MASK 0x100000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_SHARED_SHIFT 0x14
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_FULL_MASK 0x200000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_FULL_SHIFT 0x15
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_EXCLUSIVE_MASK 0x400000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_EXCLUSIVE_SHIFT 0x16
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_ERROR_MASK 0x800000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_ERROR_SHIFT 0x17
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_EARLYWRRESP_MASK 0x1000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_EARLYWRRESP_SHIFT 0x18
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_DEVICE_TYPE_MASK 0x6000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_DEVICE_TYPE_SHIFT 0x19
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_DEVICE_MASK 0x8000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_DEVICE_SHIFT 0x1b
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_CACHEABLE_MASK 0x10000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_CACHEABLE_SHIFT 0x1c
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_BURST_MASK 0x20000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_BURST_SHIFT 0x1d
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_BAR_MASK 0xc0000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2_BAR_SHIFT 0x1e

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2 0x898  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_MEMTYPE_MASK 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_MEMTYPE_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_UNUSED0_MASK 0x78
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_UNUSED0_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_TRANSIENT_MASK 0x80
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_TRANSIENT_SHIFT 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_NOALLOCATE_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_NOALLOCATE_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_OOOWR_MASK 0x200
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_OOOWR_SHIFT 0x9
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_OOORD_MASK 0x400
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_OOORD_SHIFT 0xa
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_ORDEREDWR_MASK 0x800
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_ORDEREDWR_SHIFT 0xb
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_ORDEREDRD_MASK 0x1000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_ORDEREDRD_SHIFT 0xc
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_PORTMREL_MASK 0x2000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_PORTMREL_SHIFT 0xd
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_INNERWRITETHROUGH_MASK 0x4000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_INNERWRITETHROUGH_SHIFT 0xe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_INNERTRANSIENT_MASK 0x8000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_INNERTRANSIENT_SHIFT 0xf
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_INNERSHARED_MASK 0x10000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_INNERSHARED_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_INNERCACHEABLE_MASK 0x20000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_INNERCACHEABLE_SHIFT 0x11
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_INNERNOALLOCATE_MASK 0x40000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_INNERNOALLOCATE_SHIFT 0x12
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_WRITETHROUGH_MASK 0x80000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_WRITETHROUGH_SHIFT 0x13
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_SHARED_MASK 0x100000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_SHARED_SHIFT 0x14
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_FULL_MASK 0x200000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_FULL_SHIFT 0x15
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_EXCLUSIVE_MASK 0x400000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_EXCLUSIVE_SHIFT 0x16
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_ERROR_MASK 0x800000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_ERROR_SHIFT 0x17
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_EARLYWRRESP_MASK 0x1000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_EARLYWRRESP_SHIFT 0x18
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_DEVICE_TYPE_MASK 0x6000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_DEVICE_TYPE_SHIFT 0x19
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_DEVICE_MASK 0x8000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_DEVICE_SHIFT 0x1b
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_CACHEABLE_MASK 0x10000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_CACHEABLE_SHIFT 0x1c
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_BURST_MASK 0x20000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_BURST_SHIFT 0x1d
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_BAR_MASK 0xc0000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2_BAR_SHIFT 0x1e

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2 0x898  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_MEMTYPE_MASK 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_MEMTYPE_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_UNUSED0_MASK 0x78
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_UNUSED0_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_TRANSIENT_MASK 0x80
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_TRANSIENT_SHIFT 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_NOALLOCATE_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_NOALLOCATE_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_OOOWR_MASK 0x200
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_OOOWR_SHIFT 0x9
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_OOORD_MASK 0x400
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_OOORD_SHIFT 0xa
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_ORDEREDWR_MASK 0x800
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_ORDEREDWR_SHIFT 0xb
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_ORDEREDRD_MASK 0x1000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_ORDEREDRD_SHIFT 0xc
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_PORTMREL_MASK 0x2000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_PORTMREL_SHIFT 0xd
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_INNERWRITETHROUGH_MASK 0x4000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_INNERWRITETHROUGH_SHIFT 0xe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_INNERTRANSIENT_MASK 0x8000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_INNERTRANSIENT_SHIFT 0xf
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_INNERSHARED_MASK 0x10000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_INNERSHARED_SHIFT 0x10
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_INNERCACHEABLE_MASK 0x20000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_INNERCACHEABLE_SHIFT 0x11
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_INNERNOALLOCATE_MASK 0x40000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_INNERNOALLOCATE_SHIFT 0x12
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_WRITETHROUGH_MASK 0x80000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_WRITETHROUGH_SHIFT 0x13
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_SHARED_MASK 0x100000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_SHARED_SHIFT 0x14
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_FULL_MASK 0x200000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_FULL_SHIFT 0x15
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_EXCLUSIVE_MASK 0x400000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_EXCLUSIVE_SHIFT 0x16
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_ERROR_MASK 0x800000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_ERROR_SHIFT 0x17
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_EARLYWRRESP_MASK 0x1000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_EARLYWRRESP_SHIFT 0x18
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_DEVICE_TYPE_MASK 0x6000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_DEVICE_TYPE_SHIFT 0x19
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_DEVICE_MASK 0x8000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_DEVICE_SHIFT 0x1b
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_CACHEABLE_MASK 0x10000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_CACHEABLE_SHIFT 0x1c
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_BURST_MASK 0x20000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_BURST_SHIFT 0x1d
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_BAR_MASK 0xc0000000
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2_BAR_SHIFT 0x1e

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_OWNERSTATUS0 0x900  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_OWNERSTATUS0_RGOWNERSTATUS_MASK 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_OWNERSTATUS0_RGOWNERSTATUS_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_OWNERSTATUS0_UNUSED0_MASK 0xfffffffc
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_OWNERSTATUS0_UNUSED0_SHIFT 0x2

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_GCR0 0x1000  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_GCR0_RG_OWNER_MASK 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_GCR0_RG_OWNER_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_GCR0_UNUSED0_MASK 0xf8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_GCR0_UNUSED0_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_GCR0_RG_SEC_APPS_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_GCR0_RG_SEC_APPS_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_GCR0_UNUSED1_MASK 0xfffffe00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_GCR0_UNUSED1_SHIFT 0x9

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR0 0x1010  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR0_RGSCLRDEN_APPS_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR0_RGSCLRDEN_APPS_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR0_UNUSED0_MASK 0xfffffffe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR0_UNUSED0_SHIFT 0x1

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR1 0x1014  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR1_RGCLRDEN_MASK 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR1_RGCLRDEN_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR1_UNUSED0_MASK 0xfffffff8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR1_UNUSED0_SHIFT 0x3

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR2 0x1018  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR2_RGSCLWREN_APPS_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR2_RGSCLWREN_APPS_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR2_UNUSED0_MASK 0xfffffffe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR2_UNUSED0_SHIFT 0x1

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR3 0x101c  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR3_RGCLWREN_MASK 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR3_RGCLWREN_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR3_UNUSED0_MASK 0xfffffff8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR3_UNUSED0_SHIFT 0x3

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_RACR 0x1040  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_RACR_RE_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_RACR_RE_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_WACR 0x1060  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_WACR_WE_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_WACR_WE_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_GCR0 0x1080  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_GCR0_RG_OWNER_MASK 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_GCR0_RG_OWNER_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_GCR0_UNUSED0_MASK 0xf8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_GCR0_UNUSED0_SHIFT 0x3
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_GCR0_RG_SEC_APPS_MASK 0x100
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_GCR0_RG_SEC_APPS_SHIFT 0x8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_GCR0_UNUSED1_MASK 0xfffffe00
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_GCR0_UNUSED1_SHIFT 0x9

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR0 0x1090  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR0_RGSCLRDEN_APPS_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR0_RGSCLRDEN_APPS_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR0_UNUSED0_MASK 0xfffffffe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR0_UNUSED0_SHIFT 0x1

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR1 0x1094  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR1_RGCLRDEN_MASK 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR1_RGCLRDEN_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR1_UNUSED0_MASK 0xfffffff8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR1_UNUSED0_SHIFT 0x3

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR2 0x1098  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR2_RGSCLWREN_APPS_MASK 0x1
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR2_RGSCLWREN_APPS_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR2_UNUSED0_MASK 0xfffffffe
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR2_UNUSED0_SHIFT 0x1

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR3 0x109c  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR3_RGCLWREN_MASK 0x7
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR3_RGCLWREN_SHIFT 0x0
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR3_UNUSED0_MASK 0xfffffff8
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR3_UNUSED0_SHIFT 0x3

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_RACR 0x10c0  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_RACR_RE_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_RACR_RE_SHIFT 0x0

#define regAPU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_WACR 0x10e0  /*register offset*/
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_WACR_WE_MASK 0xffffffff
#define APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_WACR_WE_SHIFT 0x0

/*----------------------------------------------------------------------
        Register Data Structures
----------------------------------------------------------------------*/

typedef struct{
    unsigned  AADEN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_gcr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_gcr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_GCR0;

typedef struct{
    unsigned  SCFGERE : 1; /* 0:0 */
    unsigned  SCLERE : 1; /* 1:1 */
    unsigned  SCFGEIE : 1; /* 2:2 */
    unsigned  SCLEIE : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  DYNAMIC_CLK_EN : 1; /* 8:8 */
    unsigned  UNUSED1 : 23; /* 31:9 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_scr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_scr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SCR0;

typedef struct{
    unsigned  CFGERE : 1; /* 0:0 */
    unsigned  CLERE : 1; /* 1:1 */
    unsigned  CFGEIE : 1; /* 2:2 */
    unsigned  CLEIE : 1; /* 3:3 */
    unsigned  UNUSED0 : 3; /* 6:4 */
    unsigned  VMIDEN : 1; /* 7:7 */
    unsigned  DYNAMIC_CLK_EN : 1; /* 8:8 */
    unsigned  UNUSED1 : 23; /* 31:9 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_cr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_cr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_CR0;

typedef struct{
    unsigned  SUVMID : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rpu_acr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rpu_acr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RPU_ACR0;

typedef struct{
    unsigned  QAD0DEN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_gcr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_gcr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_GCR0;

typedef struct{
    unsigned  CFGERE : 1; /* 0:0 */
    unsigned  CLERE : 1; /* 1:1 */
    unsigned  CFGEIE : 1; /* 2:2 */
    unsigned  CLEIE : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  DYNAMIC_CLK_EN : 1; /* 8:8 */
    unsigned  UNUSED1 : 23; /* 31:9 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_cr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_cr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_CR0;

typedef struct{
    unsigned  QAD1DEN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_gcr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_gcr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_GCR0;

typedef struct{
    unsigned  CFGERE : 1; /* 0:0 */
    unsigned  CLERE : 1; /* 1:1 */
    unsigned  CFGEIE : 1; /* 2:2 */
    unsigned  CLEIE : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  DYNAMIC_CLK_EN : 1; /* 8:8 */
    unsigned  UNUSED1 : 23; /* 31:9 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_cr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_cr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_CR0;

typedef struct{
    unsigned  NVMID : 8; /* 7:0 */
    unsigned  MV : 1; /* 8:8 */
    unsigned  PT : 1; /* 9:9 */
    unsigned  UNUSED0 : 22; /* 31:10 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_idr3;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_idr3 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR3;

typedef struct{
    unsigned  NUM_QAD : 4; /* 3:0 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  VMIDACR_EN : 8; /* 15:8 */
    unsigned  SEC_EN : 8; /* 23:16 */
    unsigned  NONSEC_EN : 8; /* 31:24 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_idr2;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_idr2 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR2;

typedef struct{
    unsigned  UNUSED0 : 16; /* 15:0 */
    unsigned  CONFIG_ADDR_WIDTH : 6; /* 21:16 */
    unsigned  UNUSED1 : 2; /* 23:22 */
    unsigned  CLIENT_ADDR_WIDTH : 6; /* 29:24 */
    unsigned  UNUSED2 : 2; /* 31:30 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_idr1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_idr1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR1;

typedef struct{
    unsigned  XPUTYPE : 2; /* 1:0 */
    unsigned  UNUSED0 : 3; /* 4:2 */
    unsigned  CLIENTREQ_HALT_ACK_HW_EN : 1; /* 5:5 */
    unsigned  UNUSED1 : 10; /* 15:6 */
    unsigned  NRG : 10; /* 25:16 */
    unsigned  UNUSED2 : 6; /* 31:26 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_idr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_idr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_IDR0;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  MINOR : 12; /* 27:16 */
    unsigned  MAJOR : 4; /* 31:28 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rev;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rev bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_REV;

typedef struct{
    unsigned  RGFREESTATUS : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rgn_freestatus0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rgn_freestatus0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_FREESTATUS0;

typedef struct{
    unsigned  ADDR_31_0 : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sear0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sear0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SEAR0;

typedef struct{
    unsigned  ADDR_63_32 : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sear1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sear1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SEAR1;

typedef struct{
    unsigned  CFG : 1; /* 0:0 */
    unsigned  CLIENT : 1; /* 1:1 */
    unsigned  CFGMULTI : 1; /* 2:2 */
    unsigned  CLMULTI : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sesr;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sesr bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESR;

typedef struct{
    unsigned  CFG : 1; /* 0:0 */
    unsigned  CLIENT : 1; /* 1:1 */
    unsigned  CFGMULTI : 1; /* 2:2 */
    unsigned  CLMULTI : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sesrrestore;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sesrrestore bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESRRESTORE;

typedef struct{
    unsigned  XPROTNS : 1; /* 0:0 */
    unsigned  AWRITE : 1; /* 1:1 */
    unsigned  XINST : 1; /* 2:2 */
    unsigned  XPRIV : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  QAD : 8; /* 15:8 */
    unsigned  ALEN : 8; /* 23:16 */
    unsigned  ASIZE : 3; /* 26:24 */
    unsigned  UNUSED1 : 2; /* 28:27 */
    unsigned  BURSTLEN : 1; /* 29:29 */
    unsigned  AC : 1; /* 30:30 */
    unsigned  UNUSED2 : 1; /* 31:31 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sesynr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sesynr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR0;

typedef struct{
    unsigned  MID : 8; /* 7:0 */
    unsigned  PID : 5; /* 12:8 */
    unsigned  BID : 3; /* 15:13 */
    unsigned  VMID : 8; /* 23:16 */
    unsigned  TID : 8; /* 31:24 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sesynr1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sesynr1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR1;

typedef struct{
    unsigned  MEMTYPE : 3; /* 2:0 */
    unsigned  UNUSED0 : 4; /* 6:3 */
    unsigned  TRANSIENT : 1; /* 7:7 */
    unsigned  NOALLOCATE : 1; /* 8:8 */
    unsigned  OOOWR : 1; /* 9:9 */
    unsigned  OOORD : 1; /* 10:10 */
    unsigned  ORDEREDWR : 1; /* 11:11 */
    unsigned  ORDEREDRD : 1; /* 12:12 */
    unsigned  PORTMREL : 1; /* 13:13 */
    unsigned  INNERWRITETHROUGH : 1; /* 14:14 */
    unsigned  INNERTRANSIENT : 1; /* 15:15 */
    unsigned  INNERSHARED : 1; /* 16:16 */
    unsigned  INNERCACHEABLE : 1; /* 17:17 */
    unsigned  INNERNOALLOCATE : 1; /* 18:18 */
    unsigned  WRITETHROUGH : 1; /* 19:19 */
    unsigned  SHARED : 1; /* 20:20 */
    unsigned  FULL : 1; /* 21:21 */
    unsigned  EXCLUSIVE : 1; /* 22:22 */
    unsigned  ERROR : 1; /* 23:23 */
    unsigned  EARLYWRRESP : 1; /* 24:24 */
    unsigned  DEVICE_TYPE : 2; /* 26:25 */
    unsigned  DEVICE : 1; /* 27:27 */
    unsigned  CACHEABLE : 1; /* 28:28 */
    unsigned  BURST : 1; /* 29:29 */
    unsigned  BAR : 2; /* 31:30 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sesynr2;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_sesynr2 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_SESYNR2;

typedef struct{
    unsigned  ADDR_31_0 : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_ear0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_ear0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_EAR0;

typedef struct{
    unsigned  ADDR_31_0 : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_ear0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_ear0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_EAR0;

typedef struct{
    unsigned  ADDR_31_0 : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_ear0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_ear0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_EAR0;

typedef struct{
    unsigned  ADDR_63_32 : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_ear1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_ear1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_EAR1;

typedef struct{
    unsigned  ADDR_63_32 : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_ear1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_ear1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_EAR1;

typedef struct{
    unsigned  ADDR_63_32 : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_ear1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_ear1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_EAR1;

typedef struct{
    unsigned  CFG : 1; /* 0:0 */
    unsigned  CLIENT : 1; /* 1:1 */
    unsigned  CFGMULTI : 1; /* 2:2 */
    unsigned  CLMULTI : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_esr;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_esr bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESR;

typedef struct{
    unsigned  CFG : 1; /* 0:0 */
    unsigned  CLIENT : 1; /* 1:1 */
    unsigned  CFGMULTI : 1; /* 2:2 */
    unsigned  CLMULTI : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_esr;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_esr bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESR;

typedef struct{
    unsigned  CFG : 1; /* 0:0 */
    unsigned  CLIENT : 1; /* 1:1 */
    unsigned  CFGMULTI : 1; /* 2:2 */
    unsigned  CLMULTI : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_esr;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_esr bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESR;

typedef struct{
    unsigned  CFG : 1; /* 0:0 */
    unsigned  CLIENT : 1; /* 1:1 */
    unsigned  CFGMULTI : 1; /* 2:2 */
    unsigned  CLMULTI : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_esrrestore;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_esrrestore bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESRRESTORE;

typedef struct{
    unsigned  CFG : 1; /* 0:0 */
    unsigned  CLIENT : 1; /* 1:1 */
    unsigned  CFGMULTI : 1; /* 2:2 */
    unsigned  CLMULTI : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_esrrestore;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_esrrestore bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESRRESTORE;

typedef struct{
    unsigned  CFG : 1; /* 0:0 */
    unsigned  CLIENT : 1; /* 1:1 */
    unsigned  CFGMULTI : 1; /* 2:2 */
    unsigned  CLMULTI : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_esrrestore;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_esrrestore bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESRRESTORE;

typedef struct{
    unsigned  XPROTNS : 1; /* 0:0 */
    unsigned  AWRITE : 1; /* 1:1 */
    unsigned  XINST : 1; /* 2:2 */
    unsigned  XPRIV : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  QAD : 8; /* 15:8 */
    unsigned  ALEN : 8; /* 23:16 */
    unsigned  ASIZE : 3; /* 26:24 */
    unsigned  UNUSED1 : 2; /* 28:27 */
    unsigned  BURSTLEN : 1; /* 29:29 */
    unsigned  AC : 1; /* 30:30 */
    unsigned  UNUSED2 : 1; /* 31:31 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_esynr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_esynr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR0;

typedef struct{
    unsigned  XPROTNS : 1; /* 0:0 */
    unsigned  AWRITE : 1; /* 1:1 */
    unsigned  XINST : 1; /* 2:2 */
    unsigned  XPRIV : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  QAD : 8; /* 15:8 */
    unsigned  ALEN : 8; /* 23:16 */
    unsigned  ASIZE : 3; /* 26:24 */
    unsigned  UNUSED1 : 2; /* 28:27 */
    unsigned  BURSTLEN : 1; /* 29:29 */
    unsigned  AC : 1; /* 30:30 */
    unsigned  UNUSED2 : 1; /* 31:31 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_esynr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_esynr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR0;

typedef struct{
    unsigned  XPROTNS : 1; /* 0:0 */
    unsigned  AWRITE : 1; /* 1:1 */
    unsigned  XINST : 1; /* 2:2 */
    unsigned  XPRIV : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  QAD : 8; /* 15:8 */
    unsigned  ALEN : 8; /* 23:16 */
    unsigned  ASIZE : 3; /* 26:24 */
    unsigned  UNUSED1 : 2; /* 28:27 */
    unsigned  BURSTLEN : 1; /* 29:29 */
    unsigned  AC : 1; /* 30:30 */
    unsigned  UNUSED2 : 1; /* 31:31 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_esynr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_esynr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR0;

typedef struct{
    unsigned  MID : 8; /* 7:0 */
    unsigned  PID : 5; /* 12:8 */
    unsigned  BID : 3; /* 15:13 */
    unsigned  VMID : 8; /* 23:16 */
    unsigned  TID : 8; /* 31:24 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_esynr1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_esynr1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR1;

typedef struct{
    unsigned  MID : 8; /* 7:0 */
    unsigned  PID : 5; /* 12:8 */
    unsigned  BID : 3; /* 15:13 */
    unsigned  VMID : 8; /* 23:16 */
    unsigned  TID : 8; /* 31:24 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_esynr1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_esynr1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR1;

typedef struct{
    unsigned  MID : 8; /* 7:0 */
    unsigned  PID : 5; /* 12:8 */
    unsigned  BID : 3; /* 15:13 */
    unsigned  VMID : 8; /* 23:16 */
    unsigned  TID : 8; /* 31:24 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_esynr1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_esynr1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR1;

typedef struct{
    unsigned  MEMTYPE : 3; /* 2:0 */
    unsigned  UNUSED0 : 4; /* 6:3 */
    unsigned  TRANSIENT : 1; /* 7:7 */
    unsigned  NOALLOCATE : 1; /* 8:8 */
    unsigned  OOOWR : 1; /* 9:9 */
    unsigned  OOORD : 1; /* 10:10 */
    unsigned  ORDEREDWR : 1; /* 11:11 */
    unsigned  ORDEREDRD : 1; /* 12:12 */
    unsigned  PORTMREL : 1; /* 13:13 */
    unsigned  INNERWRITETHROUGH : 1; /* 14:14 */
    unsigned  INNERTRANSIENT : 1; /* 15:15 */
    unsigned  INNERSHARED : 1; /* 16:16 */
    unsigned  INNERCACHEABLE : 1; /* 17:17 */
    unsigned  INNERNOALLOCATE : 1; /* 18:18 */
    unsigned  WRITETHROUGH : 1; /* 19:19 */
    unsigned  SHARED : 1; /* 20:20 */
    unsigned  FULL : 1; /* 21:21 */
    unsigned  EXCLUSIVE : 1; /* 22:22 */
    unsigned  ERROR : 1; /* 23:23 */
    unsigned  EARLYWRRESP : 1; /* 24:24 */
    unsigned  DEVICE_TYPE : 2; /* 26:25 */
    unsigned  DEVICE : 1; /* 27:27 */
    unsigned  CACHEABLE : 1; /* 28:28 */
    unsigned  BURST : 1; /* 29:29 */
    unsigned  BAR : 2; /* 31:30 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_esynr2;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad1_esynr2 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD1_ESYNR2;

typedef struct{
    unsigned  MEMTYPE : 3; /* 2:0 */
    unsigned  UNUSED0 : 4; /* 6:3 */
    unsigned  TRANSIENT : 1; /* 7:7 */
    unsigned  NOALLOCATE : 1; /* 8:8 */
    unsigned  OOOWR : 1; /* 9:9 */
    unsigned  OOORD : 1; /* 10:10 */
    unsigned  ORDEREDWR : 1; /* 11:11 */
    unsigned  ORDEREDRD : 1; /* 12:12 */
    unsigned  PORTMREL : 1; /* 13:13 */
    unsigned  INNERWRITETHROUGH : 1; /* 14:14 */
    unsigned  INNERTRANSIENT : 1; /* 15:15 */
    unsigned  INNERSHARED : 1; /* 16:16 */
    unsigned  INNERCACHEABLE : 1; /* 17:17 */
    unsigned  INNERNOALLOCATE : 1; /* 18:18 */
    unsigned  WRITETHROUGH : 1; /* 19:19 */
    unsigned  SHARED : 1; /* 20:20 */
    unsigned  FULL : 1; /* 21:21 */
    unsigned  EXCLUSIVE : 1; /* 22:22 */
    unsigned  ERROR : 1; /* 23:23 */
    unsigned  EARLYWRRESP : 1; /* 24:24 */
    unsigned  DEVICE_TYPE : 2; /* 26:25 */
    unsigned  DEVICE : 1; /* 27:27 */
    unsigned  CACHEABLE : 1; /* 28:28 */
    unsigned  BURST : 1; /* 29:29 */
    unsigned  BAR : 2; /* 31:30 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_esynr2;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_esynr2 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_ESYNR2;

typedef struct{
    unsigned  MEMTYPE : 3; /* 2:0 */
    unsigned  UNUSED0 : 4; /* 6:3 */
    unsigned  TRANSIENT : 1; /* 7:7 */
    unsigned  NOALLOCATE : 1; /* 8:8 */
    unsigned  OOOWR : 1; /* 9:9 */
    unsigned  OOORD : 1; /* 10:10 */
    unsigned  ORDEREDWR : 1; /* 11:11 */
    unsigned  ORDEREDRD : 1; /* 12:12 */
    unsigned  PORTMREL : 1; /* 13:13 */
    unsigned  INNERWRITETHROUGH : 1; /* 14:14 */
    unsigned  INNERTRANSIENT : 1; /* 15:15 */
    unsigned  INNERSHARED : 1; /* 16:16 */
    unsigned  INNERCACHEABLE : 1; /* 17:17 */
    unsigned  INNERNOALLOCATE : 1; /* 18:18 */
    unsigned  WRITETHROUGH : 1; /* 19:19 */
    unsigned  SHARED : 1; /* 20:20 */
    unsigned  FULL : 1; /* 21:21 */
    unsigned  EXCLUSIVE : 1; /* 22:22 */
    unsigned  ERROR : 1; /* 23:23 */
    unsigned  EARLYWRRESP : 1; /* 24:24 */
    unsigned  DEVICE_TYPE : 2; /* 26:25 */
    unsigned  DEVICE : 1; /* 27:27 */
    unsigned  CACHEABLE : 1; /* 28:28 */
    unsigned  BURST : 1; /* 29:29 */
    unsigned  BAR : 2; /* 31:30 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_esynr2;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_qad0_esynr2 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_QAD0_ESYNR2;

typedef struct{
    unsigned  RGOWNERSTATUS : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rgn_ownerstatus0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rgn_ownerstatus0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RGN_OWNERSTATUS0;

typedef struct{
    unsigned  RG_OWNER : 3; /* 2:0 */
    unsigned  UNUSED0 : 5; /* 7:3 */
    unsigned  RG_SEC_APPS : 1; /* 8:8 */
    unsigned  UNUSED1 : 23; /* 31:9 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_gcr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_gcr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_GCR0;

typedef struct{
    unsigned  RGSCLRDEN_APPS : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_cr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_cr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR0;

typedef struct{
    unsigned  RGCLRDEN : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_cr1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_cr1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR1;

typedef struct{
    unsigned  RGSCLWREN_APPS : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_cr2;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_cr2 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR2;

typedef struct{
    unsigned  RGCLWREN : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_cr3;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_cr3 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_CR3;

typedef struct{
    unsigned  RE : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_racr;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_racr bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_RACR;

typedef struct{
    unsigned  WE : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_wacr;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg0_wacr bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG0_WACR;

typedef struct{
    unsigned  RG_OWNER : 3; /* 2:0 */
    unsigned  UNUSED0 : 5; /* 7:3 */
    unsigned  RG_SEC_APPS : 1; /* 8:8 */
    unsigned  UNUSED1 : 23; /* 31:9 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_gcr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_gcr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_GCR0;

typedef struct{
    unsigned  RGSCLRDEN_APPS : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_cr0;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_cr0 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR0;

typedef struct{
    unsigned  RGCLRDEN : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_cr1;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_cr1 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR1;

typedef struct{
    unsigned  RGSCLWREN_APPS : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_cr2;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_cr2 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR2;

typedef struct{
    unsigned  RGCLWREN : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_cr3;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_cr3 bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_CR3;

typedef struct{
    unsigned  RE : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_racr;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_racr bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_RACR;

typedef struct{
    unsigned  WE : 32; /* 31:0 */
} _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_wacr;

typedef union{
    _apu32q2n7s1v1_2_cl36_xpu3_xpu3_rg1_wacr bitfields,bits;
    unsigned int u32All;

} APU32Q2N7S1V1_2_CL36_XPU3_XPU3_RG1_WACR;

/*----------------------------------------------------------------------
        ENUM Data Structures
----------------------------------------------------------------------*/
#endif // TITAN170_APU32Q2N7S1V1_2_CL36_H
